TUSB1210 datasheet(13/72 Pages) TI2

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6.14 Timing Requirements

PARAMETER

INPUT CLOCK

OUTPUT CLOCK

UNIT

MIN

MAX

MIN

MAX

ULPI Interface Timing

tSC, tSD

Set-up time (control in, 8-bit data in)

tSC, tHD

Hold time (control in, 8-bit data in)

1.5

tDC, tDD

Output delay (control out, 8-bit data out)

1.2

USB UART Interface Timing

tPH_DP_CON

Phone D+ connect time

100

tPH_DISC_DET

Phone D+ disconnect time

150

fUART_DFLT

Default UART signaling rate (typical rate)

9600

bps

VBAT , VDD33

VDDIO, VDD18

IORST

ICACT

VDD15

DIGPOR

CK32K

BGOK

CK32KOK

MNTR_(VDD18,VIO)_OK

MNTR_VDD33_OK

RESETN_PWR

TDELRSTPWR (61us)

TDELMNTRVIOEN (91.5us)

TDELVDD33EN (91.5us)

TMNTR (183.1us)

(input 60M) CLOCK

PLL 480M LOCKED

TPLL (300us)

DIR

TBGAP (2ms)

TPWONVDD15 (100us)

RESETB

TDELRESETB (244.1us)

TVBBDET (10us)

TCK32K_PWON (125us)

TMNTR (183.1us)

TDEL_CS_SUPPLYOK (2.84ms)

TDEL_RST_DIR (0.54ms)

Figure 6-1. TUSB1210 Power-Up Timing (ULPI Clock Input Mode)

Table 6-1. Timers and Debounce

PARAMETER

COMMENTS

MIN

TYP

MAX

UNIT

tDEL_CS_SUPPLYOK

Chip-select-to-supplies OK delay

2.84

4.10

tDEL_RST_DIR

RESETB to PHY PLL locked and DIR falling-

edge delay

0.54

0.647

tVBBDET

VBAT detection delay

µs

tBGAP

Bandgap power-on delay

tPWONVDD15

VDD15 power-on delay

100

µs

tPWONCK32K

32-KHz RC-OSC power-on delay

125

µs

tDELRSTPWR

Power control reset delay

µs

tDELMNTRVIOEN

Monitor enable delay

91.5

µs

tMNTR

Supply monitoring debounce

183.1

µs

tDELVDD33EN

VDD33 LDO enable delay

93.75

µs

tDELRESETB

RESETB internal delay

244.1

µs

tPLL

PLL lock time

300

µs

www.ti.com

TUSB1210

SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021

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