TUSB1146 datasheet(44/68 Pages) TI2

44 / 68 page

TUSB1146

SLLSFB2 – APRIL 2020

www.ti.com

Product Folder Links: TUSB1146

Submit Documentation Feedback

Table 22. USBC_EQ Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

EQ2_SEL

RH/W

0x0

If AEQ_EN = 0, this field selects EQ for USB3.1 RX2 receiver which

faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field

reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE =

1b, software can change the EQ setting for RX2p/n pins based on

value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0,

selects EQ setting for USB downstream facing port1 (RX2) when

short channel is detected. Value programmed into this field should

provide best Rx JTOL results for short channel configuration.

3-0

EQ1_SEL

RH/W

0x0

If AEQ_EN = 0, this field selects EQ for USB3.1 RX1 receiver which

faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field

reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE =

1b, software can change the EQ setting for RX1p/n pins based on

value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0,

selects EQ setting for USB downstream facing port1 (RX1) when

short channel is detected. Value programmed into this field should

provide best Rx JTOL results for short channel configuration.

8.6.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]

SS_EQ is shown in Table 23.

Return to the Summary Table.

This register controls the receiver equalization setting for the UFP (SSTX).

Table 23. SS_EQ Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

0x0

Reserved

3-0

SSEQ_SEL

RH/W

0x0

This field selects EQ for USB3.1 SSTX receiver which faces the

USB host. When EQ_OVERRIDE = 0b, this field reflects the

sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b,

software can change the EQ setting for SSTXp/n pins based on

value written to this field.

8.6.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]

USB3_MISC is shown in Table 24.

Return to the Summary Table.

Table 24. USB3_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

RXD_START_TERM

R/W

0x0

Termination setting at start of RX detection following warm reset and

at entry to SS.Inactive.

0x0 = Maintain termination. Same as tusb1046

0x1 = Turn off termination. Avoid compliance failures due to

race between local and remote rxd in case of disconnect. If

connection remains next state was polling regardless.

LFPS_EQ

R/W

0x1

Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL, and

SSEQ_SEL applies to received LFPS signal.

0x0 = EQ set to zero when receiving LFPS

0x1 = EQ set by the related registers when receiving LFPS.

U2U3_LFPS_DEBOUNCE R/W

0x0

Controls whether or not incoming LFPS is debounced or not.

0x0 = No debounce of LFPS before U2/U3 exit.

0x1 = 200us debounce of LFPS before U2/U3 exit.

TUSB1146 bảng dữ liệu(PDF) 44 Page - Texas Instruments

TUSB1146 bảng dữ liệu(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

bảng dữ liệu tải về

Link URL