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TUSB1046AI-DCI bảng dữ liệu(PDF) 23 Page - Texas Instruments |
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TUSB1046AI-DCI bảng dữ liệu(HTML) 23 Page - Texas Instruments |
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23 / 48 page ![]() 23 TUSB1046A-DCI www.ti.com SLLSF13B – JUNE 2017 – REVISED MAY 2019 Product Folder Links: TUSB1046A-DCI Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated 4. The TUSB1046A-DCI acknowledges the sub-address cycle. 5. The master terminates the write operation by generating a stop condition (P). NOTE If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write. Table 10. Register Legend ACCESS TAG NAME MEANING R Read The field may be read by software W Write The field may be written by software S Set The field may be set by a write of one. Writes of zeros to the field have no effect. C Clear The field may be cleared by a write of one. Write of zero to the field have no effect. U Update Hardware may autonomously update this field. NA No Access Not accessible or not applicable |
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