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DLPC6422ZPC bảng dữ liệu(PDF) 39 Page - Texas Instruments

tên linh kiện DLPC6422ZPC
Giải thích chi tiết về linh kiện  DLPC6422 DLP® Digital Controller
PDF  46 Pages
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DLPC6422ZPC bảng dữ liệu(HTML) 39 Page - Texas Instruments

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Table 7-4. DMD I/F, PCB Interconnect Length Matching Requirements (continued)
SIGNAL GROUP LENGTH MATCHING
DMD (LVDS)
SCA_P,SCA_N,
DDA_P(15:0),
DDA_N(15:0)
DCKA_P, DCKA_N
+/-150 (+/–3.81)
mil (mm)
DMD (LVDS)
SCB_P,SCB_N,
DDB_P(15:0),
DDB_N(15:0)
DCKB_P, DCKB_N
+/-150 (+/–3.81)
mil (mm)
Number of layer changes:
• Single-ended signals: Minimize
• Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair
typically do not change layers.
Termination requirements:
• DMD Interface—None, the DMD receiver is differentially terminated to 100 ohms internally
Connector (DMD-LVDS I/F bus only)—High Speed Connectors that meet the following requirements must be
used:
● Differential Crosstalk
<5%
● Differential Impedance
75 ohms–125 ohms
Routing requirements for right angle connectors:
When using right angle connectors, P-N pairs have to be routed in same row to minimize delay mismatch and
propagation delay difference for each row has to be accounted for on associated PCB etch lengths.
www.ti.com
DLPC6422
DLPS308A – JUNE 2025 – REVISED OCTOBER 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DLPC6422



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