PD69104B1SLASHF datasheet(13/36 Pages) MICROSEMI

13 / 36 page

4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

The following illustration shows the definition of timing for F/S-mode devices on the I2C-bus.

Figure 5 • Definition of Timing for F/S-mode Devices on the I2C-bus

3.15

UART Communication Functional Description

The UART is supported by the PD69104B1/F platform to allow communication between PD69104B1/F

IC's and an external host. The PD69104B1/F platform supports UART only as a slave. The following is a

list of features for the UART communication mode.

Slave mode

Supports 4,800 to 115,200 Baud rate, auto-learning mechanism

Supports 8-bit address

Supports 8-bit data access

Supports general broadcast transmission

8N1

8-bits data

No parity

1 stop bit

Frame transaction—header, payload, and suffix

Timeout mechanism (timeout for frame and per byte)

No successive read/write—one transaction per register (read/write)

Half-duplex implementation—Rx starts after Tx ends

A filter for glitches cancelling on the RX pin

3.15.1

The Physical Layer

The UART protocol has two data lines; the Rx, from where PD69104B1/F receives its data, and the Tx,

where data is transmitted. UART is a byte protocol in which every byte starts with a start bit and ends

with a stop bit.

The following illustration shows the UART read/write frame.

Figure 6 • UART Read/Write Frame

The data is sent in a constant frame in order to be synchronized.

The following illustration shows the master's read packet structure.

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