4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

9

3.14.6

I²C Timing Constraints

The following table lists the characteristics of the SDA and SCL bus lines for F/A-mode I2C-bus.

Table 3 • Characteristics of the SDA and SCL Bus Lines for F/A-Mode I2C-Bus

Parameter

Symbol

Standard Mode

Fast Mode

Unit

Min

Max

Min

Max

SCL clock frequency

fSCL

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

tHD;STA

4.0

0.6

µs

LOW period of the SCL clock

tLOW

4.7

1.3

µs

HIGH period of the SCL clock

tHIGH

4.0

0.6

µs

Set-up time for a repeated START

condition

tSU;STA

4.7

0.6

µs

Data hold time: for CBUS compatible

masters for I²C-bus devices

tHD;DAT

5.0

01

3.452

01

0.92

µs

Data set-up time

tSU;STA

250

1003

ns

Rise time of both SDA and SCL signals

tr

1000

20 + 0.1Cb4

300

ns

Fall time of both SDA and SCL signals

tf

300

20 + 0.1Cb4

300

ns

Set-up time for STOP condition

tSU;STO

4.0

0.6

µs

Bus free time between a STOP and

START condition

tBUF

4.7

1.3

µs

Capacitive load for each bus line

Cb

400

400

pF

Noise margin at the LOW level for each

connected device (including hysteresis)

VnL

0.1 VDD

0.1 VDD

V

Noise margin at the HIGH level for each

connected device (including hysteresis)

VnH

0.2 VDD

0.2 VDD

V

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (refers to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of

the SCL.

2. The maximum tHD;DAT has to be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

3. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU;DAT ³ 250 ns must then be met. This is in case the device does not

stretch the LOW period of the SCL signal.

4. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 ns + 250 ns = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line can be released.

Note: All values refer to V

and V

levels (see

).

IHmin

ILmax

Electrical Characteristics (see page 13)

The following illustration shows the definition of timing for F/S-mode devices on the I2C-bus.