STM32H533CE datasheet(190/231 Pages) STMICROELECTRONICS

190 / 231 page

Electrical characteristics

STM32H533xx

190/231

DS14539 Rev 1

•

VOS level set to VOS0

Refer to Section 5.3.14 for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO for SPI).

Table 110. SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tSCK

SPI clock frequency

Master receiver mode

2.7 V < VDD < 3.6 V

135/3(2)

MHz

Master receiver mode

1.71 V < VDD < 2.7 V

120/3(2)

Master transmitter mode

2.7 V < VDD < 3.6 V

135/3(2)

Master transmitter mode

1.71 V < VDD < 2.7 V

120/3(2)

Slave receiver mode

1.71 V < VDD < 3.6 V

120

Slave transmitter mode

2.7 V < VDD < 3.6 V

43(3)/6(4)

Slave transmitter mode

1.71 V < VDD < 2.7 V

41.5(3)/6(4)

tsu(NSS)

NSS setup time

Slave mode

3.5

th(NSS)

NSS hold time

Slave mode

4.5

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode

tSCK(5) - 1

tSCK(5)

tSCK(5) + 1

tsu(MI)

Data input setup time

Master mode

3.5

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

1.5

ta(SO)

Data output access time

Slave mode

6.5

tdis(SO)

Data output disable time

Slave mode

7.5

tv(SO)

Data output valid time

Slave mode

(after enable edge),

2.7 V < VDD < 3.6 V

10/26.5(4) 11.5/35.5(4)

Slave mode

(after enable edge),

1.71 V < VDD < 2.7 V

-11/61.5(4)

12/76(4)

tv(MO)

Master mode

(after enable edge)

-1.5

th(SO)

Data output hold time

Slave mode

(after enable edge)

6.5/20.5(4)

th(MO)

Master mode

(after enable edge)

1. Evaluated by characterization - Not tested in production.

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