STM32H533CE datasheet(60/231 Pages) STMICROELECTRONICS

60 / 231 page

Functional overview

STM32H533xx

60/231

DS14539 Rev 1

The digital controller handles notably:

•

USB Type-C level detection with debounce, generating interrupts

•

FRS detection, generating an interrupt

•

Byte-level interface for USB power delivery payload, generating interrupts (DMA

compatible)

•

USB power delivery timing dividers (including a clock pre-scaler)

•

CRC generation/checking

•

4b5b encode/decode

•

Ordered sets (with a programmable ordered set mask at receive)

•

Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the

capacity to detect incoming USB power delivery messages and FRS signaling.

3.43

High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)

The devices embed a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an

environment. It is specified to operate at low speeds with minimum processing and memory

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC

controller to wake up the MCU from Stop mode on data reception.

3.44

Development support

3.44.1

Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can

be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

3.44.2

Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction

and data flow inside the CPU core by streaming compressed data at a very high rate from

the devices through a small number of ETM pins to an external hardware trace port analyzer

(TPA) device.

Real-time instruction and data flow activity be recorded and then formatted for display on

the host computer that runs the debugger software. TPA hardware is commercially available

from common development tool vendors.

The ETM operates with third party debugger software tools.

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