STM32H533CE datasheet(187/231 Pages) STMICROELECTRONICS

187 / 231 page

DS14539 Rev 1

187/231

STM32H533xx

Electrical characteristics

200

USART interface characteristics

Unless otherwise specified, the parameters given in Table 107 are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 20, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5 VDD

•

I/O compensation cell activated

•

VOS level set to VOS0

Refer to Section 5.3.14 for more details on the input/output alternate function characteristics

(NSS, CK, TX, RX for USART).

Table 107. USART characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fCK

USART clock frequency

Master receiver

1.71 V < VDD < 3.6 V

MHz

Master transmitter

2.7 V < VDD < 3.6 V

31/6(2)

Master transmitter

1.71 V < VDD < 3.6 V

31/6(2)

Slave receiver

1.71 V < VDD < 3.6 V

Slave transmitter

2.7 V < VDD < 3.6 V

34/6(2)

Slave transmitter

1.71 V < VDD < 3.6 V

32/6(2)

tsu(NSS)

NSS setup time

Slave mode

tker(3) + 6.5

th(NSS)

NSS hold time

Slave mode

2.5

tw(CKH)

tw(CKL)

CK high and low time

Master mode

1/fck/2 -1

1/fck/2

1/fck/2 +1

tsu(RX)

Data input setup time

Master mode

Slave mode

3.5

th(RX)

Data input hold time

Master mode

0.5

Slave mode

1.5

tv(TX)

Data output valid time

Slave mode,

2.7 V < VDD < 3.6 V

11.5

14.5/38.5(2)

Slave mode,

1.71 V < VDD < 3.6 V

15.5/71.5(2)

Master mode,

2.7 V < VDD < 3.6 V

2.5

3/24.5(2)

Master mode,

1.71 V < VDD < 3.6 V

-3/54(2)

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