Data Sheet

ADF5611

Microwave Wideband Synthesizer with Integrated VCO

Rev. 0

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FEATURES

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RFOUT frequency range: 7300MHz to 14,600MHz

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PDIV_OUT and NDIV_OUT frequency range: 57MHz to

14,600MHz

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Fractional-N synthesizer and integer-N synthesizer modes

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Typical PFD spurious: <−105dBc

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Integrated RMS jitter at 1kHz to 100MHz integration bandwidth:

<40fs

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Normalized inband phase noise floor FOM

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Integer mode: −232dBc/Hz

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Fractional mode: −229dBc/Hz

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Maintains frequency lock over −40°C to +85°C (lock and leave)

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Low phase noise VCO

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−115dBc/Hz typical at 100kHz (7.3GHz)

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−114dBc/Hz typical at 100kHz (10GHz)

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−109dBc/Hz typical at 100kHz (14.6GHz)

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RFOUT power (typical): 6dBm

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Programmable divide by 1, 2, 4, 8, 16, 32, 64, or 128 output

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Programmable output power level

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Typical power dissipation: 1W

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48-terminal, 7 mm × 7 mm LGA package: 49 mm2

APPLICATIONS

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Military and defense

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Test equipment

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Clock generation

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Wireless infrastructure

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Satellite and very small aperture terminals (VSATs)

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Microwave radios

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

GENERAL DESCRIPTION

The ADF5611 allows implementation of fractional-N or integer-N

phase-locked loop (PLL) frequency synthesizers when used with

an external loop filter and an external reference source. The wide-

band microwave voltage controlled oscillator (VCO) design permits

frequency operation from 7300MHz to 14,600MHz at a single RF

output. A series of frequency dividers with a differential frequency

output allows operation from 57MHz to 14,600MHz. Analog and

digital power supplies for the PLL circuitry range from 3.15V to

3.45V, and the VCO supplies are between 4.75V and 5.25V.

The ADF5611 has an integrated VCO with a fundamental frequency

of 3650MHz to 7300MHz. These frequencies are internally doubled

and routed to the RFOUT pin. An additional differential output

allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16,

32, 64, or 128, allowing the user to generate RF output frequencies

as low as 57MHz. A simple 3- or 4-wire serial port interface (SPI)

provides control of all on-chip registers. To conserve power, this

divider block can be disabled when not needed through the SPI.

Likewise, the output power for both the single-ended output and the

differential output are programmable.

The integrated phase detector and Δ-Σ modulator, capable of op-

erating at up to 100MHz, permit wide loop bandwidths and fast

frequency tuning with a typical spurious level of −105dBc.

With a VCO open-loop phase noise at an 100kHz offset from

−115dBc/Hz at a 7.3GHz RFOUT to −109dBc/Hz at a 14.6GHz

RFOUT, the ADF5611 is equipped to minimize blocker effects and

to improve receiver sensitivity and transmitter spectral purity. The

low phase noise floor eliminates any contribution to modulator and

mixer noise floor in transmitter applications.