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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADF5611BCCZ bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADF5611BCCZ bảng dữ liệu(HTML) 5 Page - Analog Devices |
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5 / 48 page  Data Sheet ADF5611 SPECIFICATIONS analog.com Rev. 0 | 5 of 48 Table 1. Specifications (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments VDD3 58 mA Divide by 1 71 mA Divide by 2 77 mA Divide by 4 81 mA Divide by 8 86 mA Divide by 16 88 mA Divide by 32 90 mA Divide by 64 92 mA Divide by 128 VCOVCC 92 mA 5.0V Power-Down PLL4 2.3 µA Power down via the SPI and the PD_RDIV, PD_NDIV, PD_LD, PD_PFDCP, and PD_PFDNCLK bits, see Table 56 and Table 57 VCOVCC5 13 mA Power down via the SPI and the PD_VCO and PD_ADC bits, see Table 56 Divider5 202 μA Power down via the SPI and the PD_ODIV bit, see Table 57 VCO OPEN-LOOP PHASE NOISE RFOUT at 7.3GHz 10kHz Offset −92 dBc/Hz 100kHz Offset −115 dBc/Hz 1MHz Offset −135 dBc/Hz 10MHz Offset −155 dBc/Hz 100MHz Offset −168 dBc/Hz RFOUT at 10GHz 10kHz Offset −90 dBc/Hz 100kHz Offset −114 dBc/Hz 1MHz Offset −135 dBc/Hz 10MHz Offset −155 dBc/Hz 100MHz Offset −164 dBc/Hz RFOUT at 11GHz 10kHz Offset −89 dBc/Hz 100kHz Offset −112 dBc/Hz 1MHz Offset −132 dBc/Hz 10MHz Offset −152 dBc/Hz 100MHz Offset −164 dBc/Hz RFOUT at 14.6GHz 10kHz Offset −86 dBc/Hz 100kHz Offset −109 dBc/Hz 1MHz Offset −130 dBc/Hz 10MHz Offset −150 dBc/Hz 100MHz Offset −165 dBc/Hz PLL Integer Boundary Spurs −55 dBc LOCKED bit = 1, fREF = fPFD = 100MHz, RDIV = 1, see Figure 34 Phase Frequency Detector (PFD) Spurs −105 dBc LOCKED bit = 1, fREF = 200MHz, fPFD = 100MHz , RDIV = 2, see Figure 35 Reference Spurs −100 dBc LOCKED bit = 1, fREF = fPFD = 100MHz, RDIV = 1, see Figure 36 |
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