TPS2000C datasheet(23/50 Pages) TI2

23 / 50 page

0.100 x 0.060

& 3 18 mil vias to

inner plane 2

10 mil trace

0.100 x 0.175

& 5 18 mil vias

0.185 x 0.045

& 3 18 mil vias

0.07 x 0.08

0.08 x 0.250

0.15 x 0.15

10 mil trace

50 mil trace

IN: 0.0145in

2 area

& 2 x 0.018in vias

GND: 0.056in

2 total area

& 3 x 0.018in vias

OUT

OUT:

0.048in

2 total area

5 x 0.01in vias

0.050in trace

OUT

VIN: 0.00925in

& 3 x 0.018in vias

VOUT: 0.041in

2 total

0.050in trace

4 x 0.01in vias

GND: 0.052in

2 Total

& 3 x 0.018in vias

TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C

TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2

www.ti.com

SLVSAU6H – JUNE 2011 – REVISED APRIL 2016

Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C

TPS2069C TPS2069C-2

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Power Dissipation and Junction Temperature (continued)

Figure 43. DBV Package PCB Layout Example

Figure 44. DGN Package PCB Layout Example

Figure 45. DGK Package PCB Layout Example

As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal

MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the

RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred

board construction from the Thermal Information: SOT-23 table.

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