ADA4356ABCZ datasheet(57/61 Pages) AD

57 / 61 page

Data Sheet

ADA4356

analog.com

Rev. 0

57 of 61

Table 20. Input Clock Phase Adjust Options

INPUT CLOCK PHASE ADJUST, REGISTER 0x16,

BITS[6:4]

NUMBER of INPUT CLOCK CYCLES of PHASE DELAY

000 (Default)

001

010

011

100

101

110

111

Table 21.Output Clock Phase Adjust Options

OUTPUT CLOCK (DCO), PHASE ADJUST, REGISTER

0x16, BITS[3:0]

DCO PHASE ADJUSTMENT (APPROXIMATE DEGREES

RELATIVE to the DxAP/DxAN EDGE)

0000

0001

0010

120

0011 (Default)

180

0100

240

0101

300

0110

360

0111

420

1000

480

1001

540

1010

600

1011 through 1111

600

Serial Output Data Control (Register 0x21)

The power-on default value of this register is 0x30.

The serial output data control register programs the ADA4356 in various output data modes, to accommodate

different data capture solutions. Table 22 describes the various serialization options available in the ADA4356. Note

that, in single data rate (SDR) mode, the DCO frequency is double that of the frequency in DDR mode for a given

sample rate. In SDR mode, to stay within the capability of the DCO LVDS driver, reduce the ADC sample rate to

≤62.5MSPS to keep the DCO frequency at ≤500MHz.

User Input/Output Control 2 (Register 0x101)

The power-on default value of this register is 0x00.

Bits[7:1]—Open

Bit 0—Disable SDIO Pull-Down

Bit 0 can be set to disable the internal 31kΩ pull-down resistor on the SDIO ball (B11), which limits the loading when

many devices are connected to the SPI bus.

ADA4356ABCZ bảng dữ liệu(PDF) 57 Page - Analog Devices

ADA4356ABCZ bảng dữ liệu(HTML) 57 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

bảng dữ liệu tải về

Link URL