ADA4356ABCZ datasheet(55/61 Pages) AD

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Data Sheet

ADA4356

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Rev. 0

55 of 61

Bits[3:2]—Open

Bits[1:0]—Data Channel

Setting Bit 1 enables the data channel to receive SPI write commands. To ensure Bit 0 is configured correctly, perform

the SPI write commands, as shown in the ADC SPI Start-Up Sequence section immediately after start-up or reset.

ADC Power Modes (Register 0x08)

The power-on default value of this register is 0x00.

Bits[7:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), ADC is active.

In power-down mode (Bits[1:0] = 01), the digital datapath clocks are disabled, while the digital datapath is reset.

Outputs are disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks, and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all digital clocks and outputs (where applicable) on the chip are reset, except

the SPI port. The SPI port is always left under control of the user, that is, the port is never automatically disabled or

in reset, except by power-on reset.

Clock (Register 0x09)

The power-on default value of this register is 0x00.

Bits[7:1]—Open

Bit 0—DCS

This bit turns the DCS on and off.

Clock Divide (Register 0x0B)

The power-on default value of this register is 0x00.

Bits[7:3]—Open

Bits[2:0]—Clock Divide Ratio

Bits [2:0] are used to set the clock divide ratio.

Output Mode (Register 0x14)

The power-on default value of this register is 0x01.

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit selects the LVDS-IEEE (reduced range) option. The default setting for this bit is LVDS-ANSI. When LVDS-

ANSI or the LVDS-IEEE reduced range link is selected, the driver current is automatically selected to give the proper

output swing.

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