XIO2001IPNP datasheet(121/145 Pages) TI2

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Table 9-1. IRQ Interrupt to MSI Message Mapping

IRQ

INTERRUPT

1 MESSAGE

ENABLED

2 MESSAGES

ENABLED

4 MESSAGES

ENABLED

8 MESSAGES ENABLED

16 MESSAGES

ENABLED

IRQ0

MSI MSG #0

IRQ1

MSI MSG #0

MSI MSG #1

IRQ2

MSI MSG #0

MSI MSG #2

IRQ3

MSI MSG #0

MSI MSG #1

MSI MSG #3

IRQ4

MSI MSG #0

MSI MSG #4

IRQ5

MSI MSG #0

MSI MSG #1

MSI MSG #5

IRQ6

MSI MSG #0

MSI MSG #2

MSI MSG #6

IRQ7

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #7

IRQ8

MSI MSG #0

MSI MSG #8

IRQ9

MSI MSG #0

MSI MSG #1

MSI MSG #9

IRQ10

MSI MSG #0

MSI MSG #2

MSI MSG #10

IRQ11

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #11

IRQ12

MSI MSG #0

MSI MSG #4

MSI MSG #12

IRQ13

MSI MSG #0

MSI MSG #1

MSI MSG #5

MSI MSG #13

IRQ14

MSI MSG #0

MSI MSG #2

MSI MSG #6

MSI MSG #14

IRQ15

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #7

MSI MSG #15

The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit memory

write transactions. The system message and message number fields are included in bytes 0 and 1 of the data

payload.

9.2.1.2.1.7 PCI Bus Clocks

The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are

supported by the bridge.

Terminal PCLK66_SEL selects the default operating frequency. This signal works in conjunction with terminal

M66EN to determine the final output frequency. When PCLK66_SEL is asserted high then the clock frequency

will be either 66-MHz or 33-MHz depending on the state of M66EN. When M66EN is asserted high then the

clock frequency will be 66-MHz, when M66EN is de-asserted the clock frequency will be 33-MHz. When

PCLK66_SEL is de-asserted then the clock frequency will be either 50-MHz or 25-MHz. When M66EN is

asserted high then the clock frequency will be 50-MHz, when M66EN is de-asserted the clock frequency will be

25-MHz. The clock control register at offset D8h provides 7 control bits to individually enable or disable each PCI

bus clock output (see Section 8.4.67). The register default is enabled for all 7 outputs.

The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the

internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock

input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the

PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using the

clock control register at offset D8h (see Section 8.4.67).

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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