XIO2001IPNP datasheet(36/145 Pages) TI2

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signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately 60 kHz

during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states. The serial

EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 8-9 illustrates an

example application implementing the two-wire serial bus.

GPIO4 // SCL

GPIO3 // SDA

VDD_33

SCL

SDA

XIO2001

Serial

EEPROM

Figure 8-9. Serial EEPROM Application

8.3.8.2 Serial-Bus Interface Protocol

All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start

condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as

illustrated in Figure 8-10. The end of a requested data transfer is indicated by a stop condition, which is signaled

by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 8-10. Data on SDA must

remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of

SCL are interpreted as control signals, that is, a start or stop condition.

Figure 8-10. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are

transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data

transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so

that it remains low during the high state of the SCL signal. Figure 8-11 illustrates the acknowledge protocol.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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