XIO2001IPNP datasheet(102/145 Pages) TI2

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8.6 Memory-Mapped TI Proprietary Register Space

The programming model of the memory-mapped TI proprietary register space is unique to this device.

All bits marked with a

☆ are sticky bits and are reset by a global reset ( GRST) or the internally-generated

power-on reset. All bits marked with a(1) are reset by a PCI Express reset ( PERST), a GRST or the internally-

generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or

the internally-generated power-on reset.

Table 8-74. Device Control Memory Window Register Map

OFFSET

Reserved

Revision ID

Device control map ID

000h

Reserved

004h–03Ch

GPIO data(1)

GPIO control

(1)

040h

Serial-bus control and status(1)

Serial-bus slave address(1)

Serial-bus word address(1)

Serial-bus data(1)

044h

Serial IRQ edge control(1)

Reserved

Serial IRQ mode

control(1)

048h

Reserved

Serial IRQ status(1)

04Ch

Cache Timer Transfer Limit(1)

PFA Request Limit(1)

050h

Cache Timer Upper Limit(1)

Cache Timer Lower Limit(1)

054h

Reserved

058h–FFFh

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.6.1 Device Control Map ID Register

The device control map ID register identifies the TI proprietary layout for this device control map. The value 04h

identifies this as a PCI Express-to-PCI bridge.

Device control memory window register offset:

00h

Read-only

Default value:

04h

BIT NUMBER

RESET STATE

8.6.2 Revision ID Register

The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value

00h identifies the revision as the initial layout.

Device control memory window register offset:

01h

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

www.ti.com

102

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