UCD3138 datasheet(18/99 Pages) TI2

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Table 8-1. PMBus/SMBus/I2C Timing (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

t(SU:DAT)

Data setup time

100

t(TIMEOUT)

Error signal/detect(2)

t(LOW)

Clock low period

1.3

µs

t(HIGH)

Clock high period(3)

0.6

µs

t(LOW:SEXT)

Cumulative clock low slave extend

time(4)

Clock/data fall time

Fall time tf = 0.9 VDD to (VILmax – 0.15)

20 + 0.1

Cb(5)

300

Clock/data rise time

Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15)

20 + 0.1

Cb(5)

300

Total capacitance of one bus line

400

(1)

Fast mode, 400 kHz

(2)

The device times out when any clock low exceeds t(TIMEOUT).

(3)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(4)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Cb (pF)

Figure 8-1. I2C/SMBus/PMBus Timing Diagram

Figure 8-2. Bus Timing in Extended Mode

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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