L99PM62GXP datasheet(39/102 Pages) STMICROELECTRONICS

39 / 102 page

L99PM62GXP

Protection and diagnosis

Doc ID 17639 Rev 4

39/102

The PWM 1 / 3 channels start a PWM period with the ON phase, while the PWM 2 / 4

channels start with the OFF phase. In this way it is possible to use the 4 PWM channels in a

phase shifted way.

The Figure 21 shows this feature with a duty cycle of 25% for both PWM channels.

Figure 21.

Phase shifted PWM

3.4

Low-side driver outputs REL1, REL2

The outputs REL1, REL2 (RDSon = 2 Ω typical at 25 °C) are specially designed to drive relay

loads.

The outputs provide an active output zener clamping (45 V typical) feature for the

demagnetization of the relay coil, even though a load dump condition exists.

For fail-safe reasons the relay drivers are linked with the fail safe operation: in case of

entering the fail safe mode, the relay drivers switches off and the SPI control bits are set to

default (i.e. driver is off).

The low-side drivers switch off in case of:

●

VS over and undervoltage

●

Overcurrent

●

Overtemperature with pre warning

In case of overload or overtemperature (TSD1) condition, the drivers switches off. The

according status bit is latched and can be read and optionally cleared by SPI. The drivers

remain off until the status is cleared.

OUT4

PWM 4

Timer 2

OUTHS

PWM 3 / PWM 4

Timer 1 / Timer 2

Table 7.

PWM configuration for high-side outputs (continued)

High-side output

PWM channel

Internal timer

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