ICS1523MLF datasheet(8/21 Pages) IDT

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Video Clock Synthesizer with I2C Programmable Delay

MDS ICS1523 Z

Revision 052407

Integrated Device Technology, Inc.

Tech Support: www.idt.com/go/clockhelp

ICS1523

Section 5 Register Set Details

0xY:Z = Register Index Y(hex), bit Z

0xY:Z~Q = Register Index Y(hex), bit Z to Q

Note 3- COAST - Charge Pump Enable/Disable

The COAST input can be used to disable the charge

pump during the vertical blanking interval if the input

HSYNC input changes frequency during this time. The

charge pump is asynchronously disabled and

synchronously re-enabled on the second input HSYNC

after the disable signal goes invalid. This pin can be

connected to VSYNC or pulled to either rail if unused.

Note 4 - LOCK/REF Function

Note 5- CLK Output Divider

SSTL_3 CLK Freq. = Output Freq. / CLK Divider

Note 6 - ICP - Charge Pump Current

Increasing the charge pump current makes the loop

respond faster, raising the loop bandwidth. The typical

value when using the internal loop filter is 011.

Note 7 - VCO Divider

This is used to keep the VCO running at faster speeds

even when the output frequency is low.

VCO speed = Output Frequency * VCO Scaler

Note 8 - DPA Offset Ranges

Using the DPA above 160 MHz is not recommended.

Set DPA_OS = 0 for speeds in excess of 160 MHz to

bypass the DPA.

CP_Pol

CPen

0x0:1~0

Charge Pump Enabled If...

0 0

COAST (Pin 5) = 1

x 1

Always Enabled (Default)

1 0

COAST (Pin 5) = 0

EnPLS

IN_SEL

0x0

bit 7~6

0x7bit 7 LOCK/REF Output

0 0

0 1

PLL locked = 1 else 0

1 0

RESERVED

1 1

Post Schmitt trigger

HSYNC (pin 7) XOR

REF_Pol (0x0:2)

1 1

FOSC / (OSC _DIV +2)

0x6 bit 7,6

CLK Divider

0 0

1 (default)

0 1

1 0

1 1

0x1

Bit 2~0

Charge Pump Current (

µA)

0 0 0

0 0 1

0 1 0

0 1 1

8 (Typical Internal Filter Value)

1 0 0

1 0 1

1 1 0

1 1 1

Reserved

0x1:bit 5,4

VCO Divider

0 0

2 (default)

0 1

1 0

1 1

0x5

bit 1-0

# of DPA Delay

Elements (d)

0x4

bit 5-0

Max. (h)

Clock Range (MHz)

Min

Max

0 0

160

0 1

1 0

Reserved

1 1

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