PCM5121PW datasheet(65/121 Pages) TI2

65 / 121 page

PCM5121, PCM5122

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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

Product Folder Links: PCM5121 PCM5122

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10.5 PCM512x Power Modes

10.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM512x devices run from a 1.8-V supply. This can be generated by the internal

LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V

required by the digital core.

For systems that require 3.3-V I/O support, but lower power consumption, DVDD should be connected to 3.3 V

and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

10.5.2 Power Save Modes

The PCM512x devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM512x device automatically enters

standby mode. The DAC and line driver are also powered down.

When BCK and LRCK remain at a low level for more than 1 second, the PCM512x device automatically enters

powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition

to those disabled in standby mode.

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM512x device, or if BCK and LRCK start

correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup

sequence automatically.

10.5.3 Power Save Parameter Programming

Table 48. Power Save Registers

DESCRIPTION

Page 0, Register 2, D(4)

Software standby mode command

Page 0, Register 2, D(0)

Software power-down command

Page 0, Register 2, D(4) and D(0)

Software power-up sequence command (required after software standby or power-

down)

Page 0, Register 44, D(2:0)

Detection time of BCK and LRCK halt

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