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PCM1780, PCM1781, PCM1782

SLES132B – MARCH 2005 – REVISED AUGUST 2006

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 18

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

SRST

OVER

RSV

RSV

RSV

RSV

MUT2

MUT1

NOTE: RSV indicates a reserved bit that should be set to 0.

MUTx: Soft Mute Control

Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).

Default value: 0

MUTx = 0

Mute disabled (default)

MUTx = 1

Mute enabled

The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC

outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is

disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the

digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one

attenuator step (S dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. The step size,

S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1.

By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed

attenuation level.

OVER: Oversampling Rate Control

Default value: 0

System clock frequency = 512 fS, 768 fS, or 1152 fS

OVER = 0

×64 oversampling (default)

OVER = 1

×128 oversampling (applicable only if sampling clock frequency

≤ 24 kHz)

System clock frequency = 256 fS or 384 fS

OVER = 0

×32 oversampling (default)

OVER = 1

×64 oversampling (applicable only if sampling clock frequency

≤ 48 kHz)

System clock frequency = 128 fS, 192 fS

OVER = 0

×16 oversampling (default)

OVER = 1

×32 oversampling (applicable only if sampling clock frequency

≤ 96 kHz)

The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters.

Setting OVER = 1 is recommended under the following conditions:

•

System clock frequency = 512 fS, 768 fS, or 1152 fS, and sampling clock frequency ≤ 24 kHz

•

System clock frequency = 256 fS or 384 fS and sampling clock frequency ≤ 48 kHz

•

System clock frequency = 128 fS or 192 fS and sampling clock frequency ≤ 96 kHz

SRST: Reset

Default value: 0

SRST = 0

Reset disabled (default)

SRST = 1

Reset enabled

The SRST bit is used to enable or disable the soft reset function. The operation is the same as for the

power-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRST

function. All registers are initialized.

21

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