IS25LE512M-RLLA3:P-TY datasheet(133/189 Pages) ISSI

133 / 189 page

IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

133

Rev. A6

06/16/2025

8.44 FAST READ QUAD I/O DTR MODE OPERATION IN SPI MODE (FRQDTR, EDh or 4FRQDTR, EEh)

The FRQDTR/4FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read

mode.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O DTR

instruction.

The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4

I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency fQ2. The 8-bit address can be

latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of

clock, the other four bits at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR/4FRQDTR instruc-

tion. The address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR/4FRQDTR

instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.

• EDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• EDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• EEh is followed by a 4-byte address (A31-A0)

The sequence of issuing FRQDTR/4FRQDTR instruction is: CE# goes low → Sending FRQDTR/4FRQDTR

instruction (1-bit per clock) → 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as above

→ 6 dummy clocks (configurable, default is 6 clocks) → Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)

→ End FRQDTR/4FRQDTR operation by driving CE# high at any time during data out.

If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRQDTR/4FRQDTR execution skips command code. It saves cycles as

described in Figures 8.92 and 8.93.

When the code is different from AXh (where X is don’t care), the device exits

the AX read operation. After finishing the read operation, device becomes ready to receive a new command.

If the FRQDTR/4FRQDTR instruction is issued while an Erase, Program or Write cycle is in process is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

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