MUX508IPWR.B datasheet(30/42 Pages) TI2

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VSS

S 1A

S 2A

S 3A

GND

VDD

S 1B

S 2B

S 3B

S 4B

S 4A

Via to

ground plane

Via to

ground plane

MUX509 IPW

VSS

S 1

S 2

S 3

A 2

GND

VDD

S 5

S 6

S 7

S 8

S 4

Via to

ground plane

Via to

ground plane

MUX508IPW

MUX508, MUX509

SBAS758C – JANUARY 2016 – REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: MUX508 MUX509

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12 Layout

12.1 Layout Guidelines

Figure 45 shows an example of a PCB layout with the MUX508IPW, and Figure 46 shows an example of a PCB

layout with MUX509IPW. The guidelines provided in this section are also applicable to the SOIC MUX508ID and

MUX509ID package variants as well.

Some key considerations are:

1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure

that the capacitor voltage rating is sufficient for the VDD and VSS supplies.

2. Keep the input lines as small as possible. For the MUX509 differential signals, make sure the A inputs and B

inputs are as symmetric as possible.

3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible and only make perpendicular crossings when necessary.

12.2 Layout Example

Figure 45. MUX508IPW Layout Example

Figure 46. MUX509IPW Layout Example

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