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AX-SIP-SFEU-API bảng dữ liệu(PDF) 8 Page - ON Semiconductor |
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AX-SIP-SFEU-API bảng dữ liệu(HTML) 8 Page - ON Semiconductor |
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8 / 20 page ![]() AX−SIP−SFEU, AX−SIP−SFEU−API www.onsemi.com 8 Table 5. LOGIC Symbol Description Condition Min Typ Max Units DIGITAL INPUTS VT+ Schmitt trigger low to high threshold point VDD_IO = 3.3 V 1.55 V VT− Schmitt trigger high to low threshold point 1.25 V VIL Input voltage, low 0.8 V VIH Input voltage, high 2.0 V VIPA Input voltage range, GPIO[3:0] and GPIO[13:12] −0.5 VDD_IO V VIPBC Input voltage range, GPIO[9:4], UARTRX −0.5 5.5 V IL Input leakage current −10 10 mA RPU Programmable Pull−Up Resistance 65 kW DIGITAL OUTPUTS IOH Output Current, high GPIO[14:0], UARTTX, TXLED, RXLED, TXLED, CPULED VOH = 2.4 V 8 mA IOL Output Current, low GPIO[14:0], UARTTX, TXLED, RXLED, TXLED, CPULED VOL = 0.4 V 8 mA IOZ Tri−state output leakage current −10 10 mA AC Characteristics Table 6. TRANSMITTER (Conditions for transmitter specifications unless otherwise specified are for DVK−SIP−SFEU−1−GVK hardware configuration and at 868.130 MHz frequency.) Symbol Description Condition Min Typ Max Units SBR Signal bit rate 100 bps PTXmin Lowest Transmitter output power (Note 6) AT$CW=868130000,1,0 −1 dBm PTXmax Highest Transmitter output power (Note 6) AT$CW=868130000,1,14 13 dBm PTXstep Programming step size output power 1 dB dTXtemp Transmitter power variation vs. temperature −30°C to +85°C ±0.8 dB dTXVdd Transmitter power variation vs. VDD_IO 2.1 to 3.6 V ±0.03 dB PTXharm2 Emission @ 2nd harmonic −58 dBc PTXharm3 Emission @ 3rd harmonic −80 PTXharm4 Emission @ 4th harmonic −86 6. The output power of the AX−SIP−SFEU / AX−SIP−SFEU−API can be programmed in 1 dB steps, by changing transmitter power setting from 0 − 14. The lowest power setting is 0, which gives −1 dBm typical power at nominal temperature. The highest power setting is 14, which gives 13 dBm typical power at nominal temperature and close to 14 dBm typical power at minimum temperature. |
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