LP5569 datasheet(50/93 Pages) TI2

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LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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Table 32. LED4_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm4

R/W

00h = 0% duty cycle (default)

,,,

80h = 50% duty cycle

...

FFh = 100% duty cycle

8.6.1.18 LED5_PWM Register (Address = 1Bh) [reset = 0h]

LED5_PWM is shown in Figure 44 and described in Table 33.

Return to Summary Table.

LED5 PWM Register

This is the PWM duty cycle control for the LED5 output.

Figure 44. LED5_PWM Register

pwm5

R/W-0h

Table 33. LED5_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm5

R/W

00h = 0% duty cycle (default)

...

80h = 50% duty cycle

...

FFh = 100% duty cycle

8.6.1.19 LED6_PWM Register (Address = 1Ch) [reset = 0h]

LED6_PWM is shown in Figure 45 and described in Table 34.

Return to Summary Table.

LED6 PWM Register

This is the PWM duty cycle control for the LED6 output.

Figure 45. LED6_PWM Register

pwm6

R/W-0h

Table 34. LED6_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm6

R/W

00h = 0% duty cycle (default)

...

80h = 50% duty cycle

...

FFh = 100% duty cycle

8.6.1.20 LED7_PWM Register (Address = 1Dh) [reset = 0h]

LED7_PWM is shown in Figure 46 and described in Table 35.

Return to Summary Table.

LED7 PWM Register

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