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LP2998MA/NOPB bảng dữ liệu(PDF) 17 Page - Texas Instruments |
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LP2998MA/NOPB bảng dữ liệu(HTML) 17 Page - Texas Instruments |
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17 / 42 page ![]() VTT LP2998 PVIN VDDQ VREF AVIN VREF = 1.25V VSENSE GND + + + VDDQ = 2.5V AVIN = 3.3V or 5V VTT = 1.25V SD SD PVIN = 3.3V CIN COUT CREF VTT LP2998 PVIN VDDQ VREF AVIN VREF = 1.25V VSENSE GND + + + VDDQ = 2.5V AVIN = 2.2V to 5.5V VTT = 1.25V SD SD PVIN = 1.8V CIN COUT CREF VTT LP2998 PVIN VDDQ VREF AVIN VREF = 1.25V VSENSE GND + + + VDDQ = 2.5V VDD = 2.5V VTT = 1.25V SD SD CIN COUT CREF LP2998, LP2998-Q1 www.ti.com SNVS521K – DECEMBER 2007 – REVISED AUGUST 2014 Typical Application (continued) Figure 23. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the LP2998 has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5 V, 3.3 V, or 5 V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be encountered. Figure 24. Lower Power Dissipation SSTL-2 Implementation The third option for SSTL-2 applications in the situation that a 1.8 V rail is not available and it is not desirable to use 2.5 V, is to connect the LP2998 power rail to 3.3 V. In this situation AVIN will be limited to operation on the 3.3 V or 5 V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the LP2998 from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3 V rail. Figure 25. SSTL-2 Implementation with Higher Voltage Rails Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LP2998 LP2998-Q1 |
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