MB85RS128TY(AEC-Q100 Compliant)

8

DS501-00048-7v0-E



READ

The READ command reads FeRAM memory cell array data. Arbitrary 16 bits address and op-code of READ

are input to SI. The upper two address bits are invalid. Then, 8-cycle clock is input to SCK. SO is output

synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ

command is completed, but keeps on reading with automatic address increment which is enabled by con-

tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant

address, it rolls over to the starting address, and reading cycle keeps on infinitely.



WRITE

The WRITE command writes data to FeRAM memory cell array. WRITE op-code, arbitrary 16 bits of address

and 8 bits of writing data are input to SI. The upper two address bits are invalid. When 8 bits of writing data

is input, data is written to FeRAM memory cell array. Risen CS will terminate the WRITE command, but if

you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with

automatic address increment. When it reaches the most significant address, it rolls over to the starting

address, and writing cycle can be continued infinitely.

SO

SCK

SI

CS

00

0

0X

112

10

MSB

7

6

5

4

3

2

1

0

Data Out

MSB

High-Z

LSB

420

1

Invalid

13

12

11

10

9

825

24

23

22

21

20

19

18

31

30

29

28

27

26

OP-CODE

00

1

11

13

X3

5

16-bit Address

Invalid

LSB

20

1

3

64

5

7

SO

SCK

SI

CS

00

0

0X

112

10

MSB

7

6

5

4

3

2

1

0

Data In

MSB

High-Z

LSB

420

1

13

12

11

10

9

825

24

23

22

21

20

19

18

31

30

29

28

27

26

OP-CODE

00

0

11

13

X3

5

16-bit Address

LSB

20

1

3

64

5

7