STA680D datasheet(23/48 Pages) STMICROELECTRONICS

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DS5877 Rev 13

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STA680

Operation and general remarks

3.1

Clock schemes

The STA680 needs an external clock source to drive the internal Phase Locked Loops

(PLLs) that generate the clocks needed by the DSP cores and their peripherals.

The STA680 accepts several external reference clock sources, as listed below:



The reference clock can be supplied through the use of an external crystal or as a

digital signal coming from an external IC.



The reference clock can have different frequencies and different input pins can be

used.

The selection of the clock input mode is performed during the power-on phase of the device

by latching the value of the pins ADAT3, BLEND and DAC256X on the rising edge of the

RESET_N signal (see Section 3.2); these values shall be selected according to Table 3.

Table 3. Reference clock configuration

[ADAT3, BLEND,

DAC256X]

Clock type

Input pin

Clock frequency

(MHz)

[0,0,0] (1)

1. Default setting.

Crystal

OSC_IN

28.224

[0,0,1]

Digital

OSC_IN or CLK_IN (2)

2. When using OSC_IN pin to input the reference clock the CLK_IN pin must be connected to ground and vice

versa.

23.3472

[0,1,0]

Digital

OSC_IN or CLK_IN (2)

36.48

[0,1,1]

Digital

OSC_IN or CLK_IN (2)

2.9184

[1,0,0]

Digital

BB1_BCK(3)

3. When using BB1_BCK to input the reference clock it is suggested to connect the OSC_IN to ground and to

tie the CLK_IN pin to high value (3.3 V).

10.4

[1,0,1]

Digital

BB1_BCK(3)

10.8

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