TDA7569BLVPD datasheet(28/41 Pages) STMICROELECTRONICS

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I2C bus

TDA7569BLV

28/41

DocID023498 Rev 9

I2C bus

9.1

I2C programming/reading sequences

A correct turn on/off sequence with respect to the diagnostic timings and producing no

audible noises could be as follows (after battery connection):

–

TURN-ON: PIN2 > 4.5V --- 10 ms --- (STAND-BY OUT + DIAG ENABLE) --- 1 s

(min) --- MUTING OUT

–

TURN-OFF: MUTING IN - wait for 50 ms - HW ST-BY IN (ST-BY pin ≤ 1.2 V)

–

Car Radio Installation: PIN2 > 4.5 V --- 10ms DIAG ENABLE (write) --- 200 ms ---

I2C

read (repeat until All faults disappear).

–

OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30 ms - I2C

reading (repeat I2C reading until high-offset message disappears).

9.2

Address selection and I2C disable

When the ADSEL/I2CDIS pin is left open the I2C bus is disabled and the device can be

controlled by the STBY/MUTE pin.

In this status (no - I2C bus) the CK pin enables the HIGH-EFFICIENCY MODE (0 = STD

MODE; 1 = HE MODE) and the DATA pin sets the gain (0 = 26 dB; 1 = 16 dB).

When the ADSEL/I2CDIS pin is connected to GND the I2C bus is active with address

<1101100-x>.

To select the other I2C address a resistor must be connected to ADSEL/I2CDIS pin as

following:

0 < R < 1 kΩ: I2C bus active with address <1101100x>

11 kΩ < R < 21 kΩ: I2C bus active with address <1101101x>

40 kΩ < R < 70 kΩ: I2C bus active with address <1101110x>

R > 120 kΩ: Legacy mode

(x: read/write bit sector)

9.3

I2C bus interface

Data transmission from microprocessor to the TDA7569BLV and viceversa takes place

through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up

resistors to positive supply voltage must be connected).

9.3.1

Data validity

As shown by Figure 39, the data on the SDA line must be stable during the high period of

the clock. The HIGH and LOW state of the data line can only change when the clock signal

on the SCL line is LOW.

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