ISO1044 datasheet(11/37 Pages) TI2

11 / 37 page

6.10 Switching Characteristics

Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEVICE SWITCHING CHARACTERISTICS

tPROP(LOOP1)

Total loop delay, driver input TXD to

receiver RXD, recessive to dominant

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns; 1.71 V ≤

VCC1 ≤ 1.89 V

150

203

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤

5.5 V

150

199

tPROP(LOOP2)

Total loop delay, driver input TXD to

receiver RXD, dominant to recessive

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤

1.89 V

175

219

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤

5.5 V

175

212

tUV_RE_ENABLE

Re-enable time after Undervoltage

event

Time for device to return to normal

operation from VCC1 or VCC2 under

voltage event

300.0

µs

CMTI

Common mode transient immunity

TXD=VCC1 or GND1, VCM =

1200VPK , See Figure 7-9

kV/µs

DRIVER SWITCHING CHARACTERISTICS

tpHR

Propagation delay time, Low-to-High

TXD edge to driver recessive

See Figure 7-3 , RL = 60 Ω and CL = 100

pF; input rise/fall time (10% to 90%) on

TXD =1 ns

105

tpLD

Propagation delay time, High-to-Low

TXD edge to driver dominant

105

tsk(p)

pulse skew (|tpHR - tpLD|)

12.5

Differential output signal rise time

Differential output signal fall time

VSYM

Driver symmetry (VO(CANH) +

VO(CANL))/VCC

See Figure 7-3 and Figure 9-3 ,

RTERM =60 Ω, CL =open, CSPLIT= 4.7nF,

TXD= Dominant or receissive or toggling

at 250 kHz, 1 MHz

0.9

1.1

V/V

tTXD_DTO

Dominant time out

See Figure 7-7 , RL = 60 Ω and CL = open

1.2

3.8

RECEIVER SWITCHING CHARACTERISTICS

tpRH

Propagation delay time, bus

dominant-to-recessive input edge to

RXD high output

See Figure 7-5 , CL(RXD) = 15 pF,

130

tpDL

Propogation delay time, bus

recessive-to-dominant input edge to

RXD low output

110

Output signal rise time(RXD)

Output signal fall time(RXD)

FD TIMING PARAMETERS

tBIT(BUS)

Bit time on CAN bus output pins with

tBIT(TXD) = 500 ns

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns

435.0

530.0

Bit time on CAN bus output pins with

tBIT(TXD) = 200 ns

See Figure 7-6 , RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF; input rise/fall time (10%

to 90%) on TXD =1 ns

155.0

210.0

www.ti.com

ISO1044

SLLSFB0A – MARCH 2020 – REVISED JULY 2020

Submit Document Feedback

Product Folder Links: ISO1044

ISO1044 bảng dữ liệu(PDF) 11 Page - Texas Instruments

ISO1044 bảng dữ liệu(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

bảng dữ liệu tải về

Link URL