L9924L datasheet(58/84 Pages) STMICROELECTRONICS

58 / 84 page

SPI interface

L9924L

58/84

DocID028840 Rev 3

latches are cleared. On the rising edge of SCLK the MOSI data are sampled and the MISO

data are up-dated. The MOSI pin receives serial data from the master with MSB first.

Likewise for MISO, data is read MSB first, LSB last. A failed transmission is indicated in the

bit 23 of the MISO frame.

See next paragraphs for further details.

12.2

SPI electrical characteristics

12.2.1

CSN input

12.2.2

SCK, MOSI input

Table 36. CSN input electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

1Vin L

CSN voltage low level

1.3

2VCSNH

CSN voltage high level

2.3

VDD

3VCSNHyst

CSN hysteresis

0.4

RCSNpu

CSN pull-up resistor

Pull-up in Active/pull-

down in Stand-by.

Pull-up to internal 3.3-V

power rail.

V(CSN)=V(GND)

RCSNPU = -3.3 V/I(CSN)

-100

kΩ

Table 37. SCK, MOSI input electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

1tset

Delay time from standby to

active mode

Switching from standby to

active mode. Time until

output drivers are enabled

after CSN going to high.

160

300

µs

2Vin L

Input voltage low level

1.3

3Vin H

Input voltage high level

2.3

VDD

4Vin Hyst

Input hysteresis

0.4

5Rin PD

Input pull-down resistor

V(in) = Vin L,MAX

Rin PD = V(in)/I(in)

-100

kΩ

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