PHY2

DAC6

PHY2

ADC6

EN

200 MHz

Clock

Generator

100 MHz

CDCLVD 2106

CDCLVD2106

www.ti.com

SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011

Dual 1:6 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD2106

The CDCLVD2106 is specifically designed for driving

1

FEATURES

50-

Ω transmission lines. In case of driving the inputs

•

Dual 1:6 Differential Buffer

in single ended mode, the appropriate bias voltage

•

Low Additive Jitter: <300 fs rms

(VAC_REF) should be applied to the unused negative

in 10 kHz – 20 MHz

input pin.

•

Low Within Bank Output Skew of 45 ps (Max)

Using the control pin (EN), outputs can be either

•

Universal Inputs Accept LVDS, LVPECL,

disabled or enabled. If the EN pin is left open two

LVCMOS

buffers with all outputs are enabled, if switched to a

logical "0" both buffers with all outputs are disabled

•

One Input Dedicated for Six Outputs

(static logical "0"), if switched to a logical "1", one

•

Total of 12 LVDS Outputs, ANSI EIA/TIA-644A

buffer with six outputs is disabled and another buffer

Standard Compatible

with six outputs is enabled. The part supports a fail

•

Clock Frequency up to 800 MHz

safe function. It incorporates an input hysteresis,

which prevents random oscillation of the outputs in

•

2.375–2.625 V Device Power Supply

absence of an input signal.

•

LVDS Reference Voltage, VAC_REF, Available for

The device operates in 2.5V supply environment and

Capacitive Coupled Inputs

is characterized from –40°C to 85°C (ambient

•

Industrial Temperature Range –40°C to 85°C

temperature). The CDCLVD2106 is packaged in

•

Packaged in 6 mm x 6 mm 40-pin QFN (RHA)

small 40-pin, 6-mm × 6-mm QFN package.

•

ESD Protection Exceeds 3-kV HBM, 1-kV CDM

spacer

APPLICATIONS

•

Telecommunications/Networking

•

Medical Imaging

•

Test and Measurement Equipment

•

Wireless Communications

•

General Purpose Clocking

DESCRIPTION

The CDCLVD2106 clock buffer distributes two clock

inputs (IN0, IN1) to a total of 12 pairs of differential

LVDS clock outputs (OUT0, OUT11). Each buffer

block consists of one input and 6 LVDS outputs. The

inputs can either be LVDS, LVPECL, or LVCMOS.

Figure 1. Application Example

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2010–2011, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.