Reference

Generator

GND

LVPECL

2

2

OUTP[1,0]

OUTN[1,0]

V

CC

V

AC_REF

INP

INN

CDCLVP1102

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SCAS884D – AUGUST 2009 – REVISED DECEMBER 2015

8 Detailed Description

8.1 Overview

The CDCLVP1102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are

required to ensure correct operation of the device and to minimize signal integrity. The proper termination for

LVPECL outputs is 50

Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a

Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC

coupled configurations. These configurations are shown in Figure 12 for VCC = 2.5 V and Figure 13 for VCC = 3.3

V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver

end. If the supply voltage for the driver and receiver is different, AC coupling is required.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVP1102 is a low additive jitter universal to LVPECL fan out buffer with 2 outputs and 1 input. The

small package, low output skew, and low additive jitter make for a flexible device in demanding applications.

8.4 Device Functional Modes

The CDCLVP1102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are

required to ensure correct operation of the device and to minimize signal integrity. The proper termination for

LVPECL outputs is 50

Ω to (VCC –2) V, but this dc voltage is not readily available on PCB. Therefore, a Thevenin

equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled

configurations. These configurations are shown in Figure 12a and b for VCC = 2.5 V and Figure 13a and b for VCC

= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the

receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required.

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