L99UDL01 datasheet(70/88 Pages) STMICROELECTRONICS

70 / 88 page

Programmers guide

L99UDL01

70/88

DS12511 Rev 5

STBY1

Standby is entered when bit 13 in this register and bit 13 in register 07H are set in order.

First STBY1 must be set and then STBY2 must be set for standby to be initiated. Upon the

rising edge of CSN, when setting the second of the two bits, the device will enter standby.

Setting only one of the bits or setting the bits out of order will not cause the device to enter

standby.

Once entering Standby no communication can occur without waking the device up (CSN

falling edge).



HBDCL2

See register 07H below for description.

EXTx_VDtx

These bits set up the blanking time for VDS fault detection for the external bridges. If at turn

on the Drain-Source voltage exceeds the programmed EXTx_VDSx value during the

blanking time programmed by these bits, the fault is not triggered. The VDS fault can be

triggered after this blanking time if it persists for more than tVDS_FILTER time (1 s). The VDS

timer default setting is 1 µs.

Table 44. VDS threshold bit description

VDS threshold

Bit 8 / Bit 4

Bit 7 / Bit 3

Bit 6 / Bit 2

Bit 5 / Bit 1

Threshold

(typical)

OFF

0.25 V

0.5 V

0.75 V

1.0 V

1.25 V

1.5 V

1.75 V

2.0 V

Table 45. VDS timer bit description

VDS timer

Bit 12 / Bit 10

Bit 11 / Bit 9

Duration

1 µs

2 µs

3 µs

4 µs

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