L9347

Functional Description

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resistivity of the load is too high or the supply voltage too low. The same error is shown if the

regulator is not able to reduce the current in the load in the time tRE, so the output PWM falls

below 10%.

A clock failure (clock loss) is detected when the frequency becomes lower than f

CLK,min. All

status outputs are set on error and all power outputs are shut off. The status signals remain

in their state until the clock signal is present again. A clock failure during power on of VCC is

detected only on the regulated channels. The status outputs of the channel 1 and 2 are low

in this case.

3.7

Drift detection (regulated channels only)

The drift detection is used to compare the two regulated channels during regulation. This

“Drift” test compares the output PWM of the regulators. The resistivity of the load influences

the output PWM. The approximated formula for the output current below shows the

dependency of the load resistor to the output PWM. In this formula the energy reduction

during the recirculation is not taken into account. The real output PWM is higher. The

testmode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal

connected to the IN-inputs the output PWM must be in a range of +-14.3%. If the difference

between the two on-times is more than ±14.3% of the expected value an error is detected

and monitored by the status outputs, in the same way as described above, but a drift error

will not be registered and also not delayed with TD as other errors

Drift Definition:

Drift = PWM(1+E) - PWM (1-E) = 2PWM E

Drift * 4 < PWM (1+E)

with E >14.3% a drift is detected

E.. not correlated Error of the channels

%PWM ... Corresponding ideal output PWM to a given input PWM

A 7bit output-PWM-register is used for the comparison. The register with the lower value is

subtracted from the higher one. This result is multiplied by four and compared with the

higher value.

3.8

Other test modes

The test pin is also used to test the regulated channels in the production. With a special

sequence on this pin the power stages of the regulated channels can be controlled direct

from the input. No status feedback of the regulated channels is given. The status output is

clocked by the regulator logic. The output sequence is a indication of a proper logic

functionality. The functionality of this special test mode is shown in Table 8.

IOUT

VBAT

RL

RON

+

---------------------------- PWM



=