L9026 datasheet(14/60 Pages) STMICROELECTRONICS

14 / 60 page

6.3

Operating modes

The L9026 has four operative states:

•

Sleep mode

•

Idle mode

•

Active mode

•

Limp Home mode

The transition between operation modes is determined according to the following levels and states:

•

logic level at IDLE pin

•

logic level at INn pins

•

PWM_SPI.OUTn bits state

•

CFG_1.ACT bit state

•

MAP_PWM.OUTn and PWM_SEL.OUTn bits state

The Figure 6 represents the possible transitions in the state diagram. The description is valid if the digital POR

signal is de-asserted (indicated as POR_N in the register map). In case of POR = 0 transitions from active to idle

and from Limp Home to sleep do not guarantee switch off behavior with functional timings. A POR condition is

traced in a clear on read register in the STA_1.POR bit.

The operating mode of the device has effect on the parameters and on the behavior of L9026.

In addition, certain changes within the same operation mode can occur due to the circuitry for undervoltage

detection that monitors VBATT and VDDIO.

In case of VBATT < VBATT(UV_L) and IDLE = IN0 = IN1 = high device does not go from IDLE state to ACTIVE

state.

Starting from active state the conditions to reach sleep state are IDLE = ’0’ and INn = ‘0’ and drivers turn OFF that

is guaranteed through SW reset.

There are different options to observe the operation mode of the device:

•

status of output channels

•

status of SPI registers

•

current consumption at VBATT pin (IVBATT)

L9026

Power supply

DS13397 - Rev 9

page 14/60

L9026 bảng dữ liệu(PDF) 14 Page - STMicroelectronics

L9026 bảng dữ liệu(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

bảng dữ liệu tải về

Link URL