DRV8880PWPR datasheet(36/50 Pages) TI2

36 / 50 page

0.47 µF

0.1 µF

CPL

GND

CPH

VCP

AOUT1

AISEN

AOUT2

BOUT2

BISEN

BOUT1

GND

TRQ0

TRQ1

STEP

DIR

ENABLE

DECAY0

DECAY1

nFAULT

nSLEEP

ATE

VREF

TOFF

V3P3

0.1 µF

DRV8880

SLVSD18C – JUNE 2015 – REVISED AUGUST 2017

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Product Folder Links: DRV8880

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10 Layout

10.1 Layout Guidelines

Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended

values of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a

thick trace or ground plane connection to the device GND pin.

The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an

electrolytic.

A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM

is recommended. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.47 μF rated for 16

V is recommended. Place this component as close to the pins as possible.

Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin

as possible.

The current sense resistors should be placed as close as possible to the device pins in order to minimize trace

inductance between the pin and resistor.

10.2 Layout Example

Figure 36. Layout Recommendation

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