DRV8874PWPRG4 datasheet(23/42 Pages) TI2

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DRV8874

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SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

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Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through

via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the

package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias

are only present under the thermal pad (grid pattern with 1.2mm spacing).

Figure 20 shows an example of the simulated board for the HTSSOP package. Table 9 shows the dimensions of

the board that were varied for each simulation.

Figure 20. HTSSOP PCB model top layer

Table 9. Dimension A for 16-pin PWP package

Cu area (mm2)

Dimension A (mm)

16.43

22.35

30.68

42.42

8.2.1.2.3.1

Steady-State Thermal Performance

"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period

of time. Figure 21, Figure 22, Figure 23, and Figure 24 show how RθJA and ΨJB (junction-to-board

characterization parameter) change depending on copper area, copper thickness, and number of layers of the

PCB for the HTSSOP package. More copper area, more layers, and thicker copper planes decrease RθJA and

ΨJB, which indicate better thermal performance from the PCB layout.

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