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DRV8874PWPRG4 bảng dữ liệu(PDF) 18 Page - Texas Instruments |
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DRV8874PWPRG4 bảng dữ liệu(HTML) 18 Page - Texas Instruments |
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18 / 42 page ![]() 136 k 68 k 5 V + ± + ± + ± 44 k 156 k 5 V + ± + ± 100 k 18 DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.3.5 Pin Diagrams 7.3.5.1 Logic-Level Inputs Figure 16 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP. Figure 16. Logic-Level Input 7.3.5.2 Tri-Level Inputs Figure 17 shows the input structure for the tri-level input pin PMODE. Figure 17. PMODE Tri-Level Input 7.3.5.3 Quad-Level Inputs Figure 18 shows the input structure for the quad-level input pin IMODE. Figure 18. Quad-Level Input 7.4 Device Functional Modes The DRV887x family of devices have several different modes of operation depending on the system inputs. 7.4.1 Active Mode After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current control modes (IMODE) will be latched when the device enters active mode. |
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