L9679P datasheet(191/279 Pages) STMICROELECTRONICS

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DS11627 Rev 7

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L9679P

Safing logic

278

Safing logic

12.1

Safing logic overview

The integrated safing logic uses data from on-board and remote locations by decoding the

various SPI communications between the interfaces and the main microcontroller. The

safing logic has several programmable features enabling its ability to decode SPI

transmissions and can process data from up to 16 sensors. The operating mode involves

simple symmetrical data threshold comparisons, with the use of symmetrical or

asymmetrical counters. A high level diagram is shown in the figure below. Please note that

this top-level diagram is simplified, and references more detailed flowcharts to show a)

message decoding, b) valid data limits, c) effects of the 'combine' function, d) comparison to

thresholds and arming, and e) the setting of the 'compare complete bit. Two independent

arming outputs, ARM1INT and ARM2INT, are also mapped internally to any of the

integrated squib/pyroswitch drivers.

Figure 49. Top level safing engine flow chart

START

SPI_MSG

Received?

CS_G &

SPI_SAF_CC

Read?

MSGDEC16

Checks whether request and response

are good for each 16-bit safing record,

taking into account IF bit. Determines

DATA taking into account SPIFLDSEL

bit

CC_READ

COMPARE

Compare DATA to thresholds , update

event counters

Updates event counters

if no data received,

clears CC bits,

DCUIC Safing Logic

Top Level

VALDAT

Checks whether data is within range if

configured

COMBINE

Converts data to be compared into

combined data (sum and difference) if

configured

ARMING

set ARM1INT and

ARM2INT, manage dwell

timers

MSGDEC32

Checks whether request and response

are good for each 32-bit safing record,

taking into account IF bit.

GAPGPS02290

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