DAC7750IPWPR datasheet(30/56 Pages) TI2

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8.5 Programming

Table 8-11 describes the available commands and registers on the DACx750 devices. No operation, read

operation, and watchdog timer refer to commands and are not explicit registers. For more information on these

commands, see Section 8.5.1.3 and Section 8.3.8.

8.5.1 Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates

at clock rates of up to 30 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP)

standards. The SPI communication command consists of a write address byte and a data word for a total of 24

bits. The timing for the digital interface is illustrated in Figure 7-1 and Figure 7-2.

8.5.1.1 SPI Shift Register

The default frame is 24 bits wide (see Section 8.3.9 for 32-bit frame mode) and begins with the rising edge of

SCLK that clocks in the MSB. The subsequent bits are latched on successive rising edges of SCLK. The default

24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 8-7.

Table 8-7. Default SPI Frame

BIT 23:BIT 16

BIT 15:BIT 0

Address byte

Data word

The host processor must issue 24 bits before it issues a rising edge on the LATCH pin. Input data bits are

clocked in regardless of the LATCH pin and are unconditionally latched on the rising edge of LATCH. By default,

the SPI shift register resets to 0x000000 at power on or after a reset.

8.5.1.2 Write Operation

A write operation is accomplished when the address byte is set according to Table 8-8. For more information on

the DACx750 registers, see Section 8.6.

Table 8-8. Write Address Functions

ADDRESS

BYTE

(HEX)

FUNCTION

No operation (NOP)

Write DAC Data register

Write control register

Write reset register

Write configuration register

Write DAC gain calibration register

Write DAC zero calibration register

Watchdog timer reset

CRC error reset

DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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