DAC7750IPWPR datasheet(22/56 Pages) TI2

22 / 56 page

0.00

Supply (V)

Specified Supply

Voltage Range

No Power-On Reset

Supply Max.

Supply Min.

Power-On Reset

POR Threshold

Undefined

Undefined Operation Threshold

Figure 8-3. Relevant Voltage Levels for POR Circuit

For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply min) to 5.5 V

(supply max). For the DVDD supply region between 2.4 V (undefined operation threshold) and 0.8 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the

DVDD supply below 0.8 V (POR threshold), the internal POR resets if the supply voltage remains less than 0.8 V

for approximately 1 ms.

For the AVDD supply, no internal POR occurs for nominal supply operation from 10 V (supply min) to 36 V

(supply max). For AVDD supply voltages between 8 V (undefined operation threshold) and 1 V (POR threshold),

the internal POR circuit may or may not provide a reset over all temperature conditions. For the AVDD supply

below 1 V (POR threshold), the internal POR resets if the supply voltage remains less than 1 V for approximately

1 ms. In case the DVDD or AVDD supply drops to a level where the internal POR signal is indeterminate, either

power cycle the device, or toggle the LATCH pin and then perform a software reset. Both options initialize the

internal circuitry to a known state and provide proper operation.

8.3.7 Alarm Detection

These devices also provide an alarm detection feature. When one or more of following events occur, the ALARM

pin goes low:

• The current output load is in open circuit,

• The voltage at IOUT reaches a level where accuracy of the output current is compromised. This condition

is detected by monitoring internal voltage levels of the IOUT circuitry and is typically below the specified

compliance voltage headroom (defined as the voltage drop between the AVDD and IOUT pins) minimum of 2

• The die temperature exceeds 142°C,

• The SPI watchdog timer exceeds the timeout period (if enabled), or

• The SPI frame error CRC check encounters an error (if enabled).

When the ALARM pins of multiple DACx750 devices are connected together to form a wired-AND function, the

host processor must read the status register of each device to know all the fault conditions that are present. Note

that the thermal alarm has hysteresis of approximately 18°C. After being set, the alarm only resets when the die

temperature drops below 124°C.

DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

www.ti.com

Submit Document Feedback

Product Folder Links: DAC7750 DAC8750

DAC7750IPWPR bảng dữ liệu(PDF) 22 Page - Texas Instruments

DAC7750IPWPR bảng dữ liệu(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL