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STM32WL33C8 bảng dữ liệu(PDF) 27 Page - STMicroelectronics |
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STM32WL33C8 bảng dữ liệu(HTML) 27 Page - STMicroelectronics |
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27 / 91 page  3.22 Serial peripheral interface (SPI/I2S) The STM32WL33xx embeds two serial peripheral interfaces (SPIs), the SPI1 and SPI3. The SPI3 supports I2S protocol in addition to SPI features. SPI1 does not support I2S. SPI or I2S mode is selectable by software. SPI Motorola mode is selected by default after a device reset. The SPI interfaces allow communication at up to 32 Mbit/s in both master and slave modes. The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master, and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration. The Inter-IC sound (I2S) protocol is also a synchronous serial communication interface. It can operate in slave or master mode with full duplex and half-duplex communication. It can address four different audio standards including the Philips I2S standard, the MSB- and LSB-justified standards and the PCM standard. The main SPI features are: • Master or slave operation • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) • 4-bit to 16-bit data size selection • Multimaster mode capability • 8 master mode baud rate prescalers up to fPCLK/2 • Slave mode frequency up to fPCLK/2 • NSS management by hardware or software for both master and slave: dynamic change of master/slave operations • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Dedicated transmission and reception flags with interrupt capability • SPI bus busy status flag • SPI Motorola support • Hardware CRC feature for reliable communication: – CRC value can be transmitted as last byte in Tx mode – automatic CRC error checking for last received byte • Master mode fault, overrun flags with interrupt capability • CRC error flag • Two 32-bit embedded Rx and Tx FIFOs with DMA capability • SPI TI mode support • DMA capability for transmission and reception (16-bit wide) The main I2S features are: • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) • Data format may be 16-bit, 24-bit or 32-bit • Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data frame) by audio channel • Programmable clock polarity (steady state) • Underrun flag in slave transmission mode, overrun flag in reception mode (master and slave) and Frame Error Flag in reception and transmitter mode (slave only) • 16-bit register for transmission and reception with one data register for both channel sides STM32WL33xx Functional overview DS14221 - Rev 5 page 27/91 |
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