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STM32WL33C8 bảng dữ liệu(PDF) 26 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Multiprotocol LPWAN 32-bit MCU Arm® Cortex®-M0 2(G)FSK, 4(G)FSK, ASK, D-BPSK, up to 256KB flash, 32KB SRAM
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3.21
Low power universal asynchronous receiver transmitter (LPUART)
The low power universal asynchronous receiver transmitted (LPUART) is an UART which allows bidirectional
UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART
communications up to 9600 baud/s. Higher baud rates can be reached when the LPUART is clocked by clock
sources different from the LSE clock.
Even when the microcontroller is in stop mode, the LPUART can wait for an incoming UART frame while having
an extremely low energy consumption. The LPUART includes all necessary hardware support to make
asynchronous serial communications possible with minimum power consumption.
It supports half-duplex single wire communications and modem operations (CTS/RTS). It also supports
multiprocessor communications.
DMA (direct memory access) can be used for data transmission/reception.
The main features are:
•
Full-duplex asynchronous communications
•
NRZ standard format (mark/space)
•
Programmable baud rate
•
From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
•
Higher baud rates can be achieved by suing a higher frequency clock source
•
Two internal FIFOs for transmit and receive data, that can be enabled/disabled by software. FIFOs come
with status flags for FIFOs states.
•
Dual clock domain allowing:
–
UART functionality and wakeup from stop mode
–
convenient baud rate programming independent from the PCLK reprogramming
•
Programmable data word length (7 or 8 or 9 bits)
•
Programmable data order with MSB-first or LSB-first shifting
•
Configurable stop bits (1 or 2 stop bits)
•
Single-wire half-duplex communications
•
Continuous communications using DMA
•
Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
•
Separate enable bits for transmitter and receiver
•
Separate signal polarity control for transmission and reception
•
Swappable Tx/Rx pin configuration
•
Hardware flow control for modem and RS-485 transceiver
•
Transfer detection flags:
–
receive buffer full
–
transmit buffer empty
–
busy and end-of-transmission flags
•
Parity control:
–
transmits parity bit
–
checks parity of received data byte
•
Four error detection flags:
–
overrun error
–
noise detection
–
frame error
–
parity error
•
Interrupt sources with flags
•
Multiprocessor communications: the LPUART enters mute mode if the address does not match
•
Wakeup from mute mode (by idle line detection or address mark detection)
STM32WL33xx
Functional overview
DS14221 - Rev 5
page 26/91



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