MB85RS2MTA datasheet(2/40 Pages) RAMXEED

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MB85RS2MTA

DS501-00032-6v1-E



PIN ASSIGNMENT



PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name

Functional description

Chip Select pin

This is an input pin to make chips select. When CS is “H” level, device is in deselect

(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this

time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before

inputting op-code. The Chip Select pin is pulled up internally to the VDD pin.

Write Protect pin

This is a pin to control writing to a status register. The writing of status register (see “

STATUS REGISTER”) is protected in related with WP and WPEN. See “WRITING

PROTECT” for detail.

HOLD

Hold pin

This pin is used to interrupt serial input/output without making chips deselect. When

HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

do not care. See “HOLD OPERATION” for detail.

SCK

Serial Clock pin

This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising

edge, SO is output synchronously to a falling edge.

Serial Data Input pin

This is an input pin of serial data. This inputs op-code, address, and writing data.

Serial Data Output pin

This is an output pin of serial data. Reading data of FeRAM memory cell array and status

VDD

Supply Voltage pin

VSS

Ground pin

(TOP VIEW)

(

8-pin plastic SOP, 150mil)

VSS

VDD

SCK

HOLD

(TOP VIEW)

(

8-pin plastic SOP, 208mil)

VSS

VDD

SCK

HOLD

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