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STAMP0TR bảng dữ liệu(PDF) 13 Page - STMicroelectronics

tên linh kiện STAMP0TR
Giải thích chi tiết về linh kiện  Microphone array processor with TDM output and recombination for wide dynamic range microphones
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STAMP0TR bảng dữ liệu(HTML) 13 Page - STMicroelectronics

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STAMP0
Architecture
DocID028639 Rev 1
13/62
4
Architecture
In the following sections the STAMP0 internal functional blocks depicted in Figure 2: "Block
diagram" are described in detail.
4.1
PDM sampling interface
The STAMP0 has four PDM data interface lines to permit up to:
•
8 single-membrane digital microphones (with shared data lines)
•
4 dual-membrane digital microphones (such as MP34DTW01) with the internal
microphone recombination features enabled
•
A combination of single and dual-membrane microphones
The device will accept 64 Fs serial data in, where Fs is the audio bandwidth used in the
processing section (for example 2.8224 MHz in case of 44.1 kHz or 3.072 MHz in case of
48 kHz).
The four PDM inputs can be sampled either at the rising or at the falling edge of the PDM
sampling interface clock (PDM_SMP_CLK). As depicted in Figure 3: "PDM interface
sampling control and usage example", for each single PDM line, the desired edge can be
selected using the SMPMxy I²C register (Reg. 0x2E, bits 7:0).
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Product(s)
- Obsolete
Product(s)



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