STA382BWSTR datasheet(46/172 Pages) STMICROELECTRONICS

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STA382BWS

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Doc ID 022784 Rev 1

6.1

CLK register (addr 0x00)

Table 15.

CLK register

6.2

STATUS register (addr 0x01)

CLK_CFG[3:0]

Reserved

I2S

Bit

R/W

RST

Name

Description

7R/W

CLK_CFG[3:0]

0000: 44.1/48 kHz BITCLK = 64 Fs

0001: 32 kHz BITCLK = 64 Fs

0010: 96 kHz BITCLK = 64 Fs

0011: 48/44.1/32 kHz MCK = 256 Fs

others: clock configuration depends on IR/MCS bits

6R/W

5R/W

4R/W

0R/W

I2S

‘0’ = SAI configured in I2S mode

‘1’ = SAI configuration depends on CONFB register

status

FAULT

DRCCRC

EQCRC

BADPWM

Reserved

I2SERR

PLLUL

Table 16.

STATUS register

Bit

R/W

RST

Name

Description

FAULT(1)

Fault status is set to 1 once the power bridge goes to tri-state mode.

‘0’ = the power bridge is in fault condition

‘1’ = the power bridge is in normal condition

DRCCRC

‘0’ = normal operation

‘1’ = CRC error on DRC BIQUADS

EQCRC

‘0’ = normal operation

‘1’ = CRC error on BIQUADS

BADPWM

‘0’ = normal operation

‘1’ = PWM outputs are invalid

I2SERR

‘0’ = normal operation

‘1’ = SAI interface error detected (see Section 6.14:

Configuration register B (addr 0x12))

PLLUL

‘0’ = PLL is locked

‘1’ = PLL is not locked

Obsolete

Product(s)

- Obsolete

Product(s)

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