REF2925 datasheet(21/62 Pages) TI2

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SAR

ADC

SPI

AINP

AINN

GND

AVDD

DVDD

REF

DOUT

SCLK

CONVST

DIN

Sample

and

Hold

REF

GND

AGND

REFM

DGND

ADC

ADS8881

www.ti.com

SBAS547D – MAY 2013 – REVISED AUGUST 2015

Product Folder Links: ADS8881

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10 Detailed Description

10.1 Overview

The ADS8881 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) from

a 16- and 18-bit device family. This compact device features high performance. Power consumption is inherently

low and scales linearly with sampling speed. The architecture is based on charge redistribution that inherently

includes a sample-and-hold (S/H) function.

The ADS8881 supports a true-differential analog input across two pins (INP and INN). When a conversion is

initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in

progress, both the INP and INN inputs are disconnected from the internal circuit.

The ADS8881 uses an internal clock to perform conversions. The device reconnects the sampling capacitors to

the INP and INN pins after conversion and then enters an acquisition phase. During the acquisition phase, the

device is powered down and the conversion result can be read.

The device digital output is available in SPI-compatible format, thus making interfacing with microprocessors,

digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) easy.

10.2 Functional Block Diagram

Figure 45 shows the detailed functional block diagram for the device.

Figure 45. Detailed Block Diagram

10.3 Feature Description

10.3.1 Analog Input

As shown in Figure 45, the device features a differential analog input. Both positive and negative inputs are

individually sampled on 55-pF sampling capacitors and the device converts for the voltage difference between

the two sampled values: VINP – VINN.

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