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ADS7044IDCUT bảng dữ liệu(PDF) 22 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  ADS7044 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC
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SCLK(fCLK-CAL)
CS
Sample
N
0
0
D11
D10
SDO
Data for Sample N
D1
D0
15
16
18
17
32
31
Sample
N+1
tCONV
tCAL
tACQ
tPH_CS
tSU_CSCK
tD_CKCS
ADS7044
SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
www.ti.com
8.4.1.2 Offset Calibration During Normal Operation
The offset can also be calibrated during normal device operation. Offset calibration can be done during normal
device operation if at least 32 SCLKs are provided in one serial transfer frame. During the first 14 SCLKs, the
device converts the sample acquired on the CS falling edge and provides data on the SDO output. The device
initiates the offset calibration on the 17th SCLK falling edge and calibration is completed on the 32nd SCLK
falling edge. The SDO output remains low after the 14th SCLK falling edge and SDO goes to 3-state after CS
goes high. If the device is provided with less than 32 SCLKs during a serial transfer frame, the OCR is not
updated. Table 3 provides the timing parameters for offset calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in OCR. The conversion
result adjusted with the value stored in the OCR is provided by the device on the SDO output. Figure 38 shows
the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MIN
TYP
MAX
UNIT
fCLK-CAL
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
16
MHz
fCLK-CAL
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
12
MHz
tCAL
Calibration time during normal operation
16 tSCLK
ns
tACQ
Acquisition time
200
ns
tPH_CS
CS high time
tACQ
ns
Figure 38. Offset Calibration During Normal Operation Timing Diagram
22
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Product Folder Links: ADS7044



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